Zeno Ziyu XIE

Ph.D. Student, Information Engineering
Logo The Chinese University of Hong Kong (Year of Admin: 2025)

Hello, I'm Zeno Ziyu XIE, a Ph.D. student at The Chinese University of Hong Kong (CUHK), majoring in Information Engineering. My academic interests lie in Machine Learning, Federated Learning, Optimization, and Communication Systems.

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Education Background
  • The Chinese University of Hong Kong
    The Chinese University of Hong Kong
    The Faculty of Engineering
    Aug. 2025 - Present
    • Ph.D. Student in Information Engineering (IE)
  • The Chinese University of Hong Kong, Shenzhen
    The Chinese University of Hong Kong, Shenzhen
    School of Science and Engineering (SSE)
    Sep. 2021 - Jul. 2025
    • B.Eng. in Electronic and Information Engineering (EIE)
    • Substream: Computer Engineering (CE)
Researching Experience
  • ERG4901 SSE Capstone Project
    ERG4901 SSE Capstone Project
    The Chinese University of Hong Kong, Shenzhen
    Sep. 2024 - Dec. 2024
    • Topic: 'Coverage Analysis for Ground to Air Communications in 5G.'
  • ERG2081 Independent Study Project
    ERG2081 Independent Study Project
    The Chinese University of Hong Kong, Shenzhen
    Sep. 2023 - Dec. 2023
    • Topic: "Implementing a federated learning frame with a Block Coordinate Descent (BCD) optimizer." Reduced communication costs by integrating the BCD algorithm into the update process of federated learning. Conducted a comparative analysis of the BCD algorithm versus the traditional FedAvg algorithm.
  • Undergraduate Research Assistant
    Undergraduate Research Assistant
    The Chinese University of Hong Kong, Shenzhen
    Jun. 2022 - Aug. 2022
    • Topic: "Studying the impact of parasitic capacitance on phase-change-memory based neuromorphic circuits." Analyzed the effects of parasitic capacitance on synaptic firing and weight updating. Estimated bitline load adhering to the design constraints derived from parasitic capacitance effects.
Working Experience
  • OSA Student Journalists Association
    OSA Student Journalists Association
    The Chinese University of Hong Kong, Shenzhen
    • Executive Editor of Website Operations Group
      Sep. 2021 - May. 2025
  • SSE Student Help Room Preceptor
    SSE Student Help Room Preceptor
    The Chinese University of Hong Kong, Shenzhen
    • Preceptor for CSC1002 (Python Laboratory)
      Jan. 2024 - May. 2024
    • Preceptor for CSC1001 (Intro. to Python)
      Sep. 2023 - Dec. 2023
  • Undergraduate Student Teaching Fellows
    Undergraduate Student Teaching Fellows
    The Chinese University of Hong Kong, Shenzhen
    • Teaching Assistant, CSC3170 (Database System)
      Jan. 2025 - May. 2025
    • Teaching Assistant, CSC3150 (Operating System)
      Jan. 2024 - May. 2024
    • Teaching Assistant, CSC3050 (Computer Architecture)
      Sep. 2023 - Dec. 2023
    • Teaching Assistant, MAT1008 (Advanced Mathematics)
      Sep. 2022 - Dec. 2022
Scholarships and Honors
  • Honors
    • (2024-25) 2025 SSE Dean's Award for Outstanding Students
      May. 2025
    • (2024-25) 2025 Outstanding Graduates Award of Muse College
      Apr. 2025
    • (2023-24) CUHKSZ, Excellent Student Award
      Jan. 2025
    • (2023-24) CUHKSZ, Campus Promotion Talent Award
      Nov. 2024
    • (2023-24) SDS, Excellent USTF Award, 2nd Class
      Nov. 2024
    • (2023-24) MLA: Whole-Person Development Star - Gold
      Nov. 2024
    • (2023-24) SSE, Dean's List Award
      Sep. 2024
    • (2022-23) CUHKSZ, Excellent Student Award
      Jan. 2024
    • (2022-23) SSE, Dean's List Award
      Sep. 2023
    • (2021-22) SSE, Dean's List Award
      Sep. 2022
  • Scholarships
    • (2023-24) SSE, AP Scholarship, Class B
      Dec. 2024
    • (2022-23) SSE, AP Scholarship, Class C
      Dec. 2023
    • (2021-22) SSE, AP Scholarship, Class C
      Dec. 2022
    • (2021-24) Muse College, Bowen II Scholarship
      Sep. 2021
Competition Awards
  • Competition Awards
    • (2024 USA) Mathematical Contest In Modeling (MCM), Honorable Mention, The Consortium for Mathematics and Its Applications (COMAP)
      May. 2024
    • (2022) MathorCup Undergraduate Mathematical Modeling Challenge, Second Prize, Chinese Society of Optimization, Overall Planning and Economic Mathematics
      Mar. 2023
    • (2022) China Undergraduate Mathematical Contest in Modeling, Guangdong Provincial Contest, Third Prize, China Society for Industrial and Applied Mathematics (CSIAM)
      Mar. 2023
Selected Publications (view all )
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes

Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)

2nd International Symposium of Electronics Design Automation (ISEDA) 2024

The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

[Link] [PDF]

Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes

Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)

2nd International Symposium of Electronics Design Automation (ISEDA) 2024

The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

[Link] [PDF]