Ziyu XIE

Ph.D. Student in Information Engineering
Logo The Chinese University of Hong Kong (Year of Admin: 2025)

Hello, I'm Ziyu (Zeno) XIE, currently a Ph.D. student at The Chinese University of Hong Kong (CUHK), majoring in Information Engineering (IE). I obtained my B.Eng. degree from The Chinese University of Hong Kong, Shenzhen (CUHK-Shenzhen) in August 2025. My academic interests lie in Communication System, Machine Learning, and Artificial Intelligence.

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Education Background
  • The Chinese University of Hong Kong
    The Chinese University of Hong Kong
    The Faculty of Engineering
    Aug. 2025 - Present
    • Ph.D. Student in Information Engineering (IE)
  • The Chinese University of Hong Kong, Shenzhen
    The Chinese University of Hong Kong, Shenzhen
    School of Science and Engineering (SSE)
    Sep. 2021 - Jul. 2025
    • B.Eng. in Electronic and Information Engineering (EIE)
    • Substream: Computer Engineering (CE)
Research Experience
  • MSFC: Flight Route Coverage Algorithm Based on Mean Shift Clustering
    MSFC: Flight Route Coverage Algorithm Based on Mean Shift Clustering
    ERG4901 SSE Capstone Project - The Chinese University of Hong Kong, Shenzhen
    Sep. 2024 - Dec. 2024
    • Developed a mean shift clustering-based algorithm to optimize 5G base station beam configurations, significantly enhancing aerial signal coverage along specified flight routes while reducing energy consumption.
  • Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits Under Advanced Technology Nodes
    Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits Under Advanced Technology Nodes
    Research Assistant - The Chinese University of Hong Kong, Shenzhen
    Jun. 2022 - Mar. 2024
    • Estimated and analyzed the impact of parasitic capacitance on the maximum number of synapses in PCM-based neuromorphic circuits under advanced technology node scaling, proposing a methodology for rapid design evaluation.
Working Experience
  • Postgraduate Teaching Assistant
    Postgraduate Teaching Assistant
    The Chinese University of Hong Kong
    • Teaching Assistant, ENGG1110E (Problem Solving by Programming)
      Sep. 2025 - Present
  • Undergraduate Student Teaching Fellows
    Undergraduate Student Teaching Fellows
    The Chinese University of Hong Kong, Shenzhen
    • Teaching Assistant, CSC3170 (Database System)
      Jan. 2025 - May. 2025
    • Teaching Assistant, CSC3150 (Operating System)
      Jan. 2024 - May. 2024
    • Teaching Assistant, CSC3050 (Computer Architecture)
      Sep. 2023 - Dec. 2023
    • Teaching Assistant, MAT1008 (Advanced Mathematics)
      Sep. 2022 - Dec. 2022
  • SSE Student Help Room Preceptor
    SSE Student Help Room Preceptor
    School of Science and Engineering - The Chinese University of Hong Kong, Shenzhen
    • Preceptor for CSC1002 (Python Laboratory)
      Jan. 2024 - May. 2024
    • Preceptor for CSC1001 (Introduction to Programming Methodology)
      Sep. 2023 - Dec. 2023
  • OSA Student Journalists Association
    OSA Student Journalists Association
    Office of Student Affairs - The Chinese University of Hong Kong, Shenzhen
    • Executive Editor of Website Operations Group
      Sep. 2023 - May. 2025
    • Senior Editor of Website Operations Group
      Sep. 2022 - Aug. 2023
    • Art Editor and Website Operator of Website Operations Group
      Sep. 2021 - Aug. 2022
Honors and Awards
  • Honors
    • (2024-25) 2025 SSE Dean's Award for Outstanding Students
      May. 2025
    • (2024-25) 2025 Outstanding Graduates Award of Muse College
      Apr. 2025
    • (2023-24) CUHKSZ, Excellent Student Award
      Jan. 2025
    • (2023-24) Master's List Award of Muse College: Whole-Person Development Star - Gold Prize
      Nov. 2024
    • (2023-24) CUHKSZ, Campus Promotion Talent Award
      Nov. 2024
    • (2023-24) SDS, Excellent USTF Award, 2nd Class
      Nov. 2024
  • Scholarships
    • (2023-24) SSE, AP Scholarship, Class B
      Dec. 2024
    • (2022-23) SSE, AP Scholarship, Class C
      Dec. 2023
    • (2021-22) SSE, AP Scholarship, Class C
      Dec. 2022
    • (2021-24) Muse College, Bowen II Scholarship
      Sep. 2021
Selected Publications (view all )
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes

Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)

2nd International Symposium of Electronics Design Automation (ISEDA) 2024

The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

[Link] [PDF]

Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes

Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)

2nd International Symposium of Electronics Design Automation (ISEDA) 2024

The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

[Link] [PDF]