Ziyu XIE

Undergraduate Student, Electronic and Information Engineering
Logo B.Eng., The Chinese University of Hong Kong, Shenzhen (2025)

Hello, I'm Ziyu XIE, an undergraduate student at the Chinese University of Hong Kong, Shenzhen (CUHKSZ), majoring in Electronic and Information Engineering. My academic interests lie in Machine Learning, Optimization, and Communication Systems.

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Education Background
  • The Chinese University of Hong Kong, Shenzhen
    The Chinese University of Hong Kong, Shenzhen
    B.Eng. in Electronic and Information Engineering
    Sep. 2021 - Jul. 2025
  • Nanjing Number One Middle School
    Nanjing Number One Middle School
    A young high school student
    Sep. 2018 - Jul. 2021
Scholarships & Honors
  • CHUKSZ, Excellent Student Award
    2023
  • SSE, Academic Performance Scholarship, Class C
    2022
  • SSE, Dean's List Award
    2022
  • SSE, Academic Performance Scholarship, Class C
    2021
  • SSE, Dean's List Award
    2021
  • Muse, Bowen II Scholarship
    2021 - 2024
Competition Awards
  • Mathematical Contest in Modeling (MCM), Honorable Mention
    2024
  • MathorCup College Mathematical Modeling Challenge - Big Data Competition, Undergraduate Group, Second Prize
    2022
  • National College Student Mathematical Modeling Competition, Guangdong Provincial Contest, Third Prize
    2022
Teaching Experience
  • Undergraduate Student Teaching Fellows
    Undergraduate Student Teaching Fellows
    The Chinese University of Hong Kong, Shenzhen
    • Teaching Assistant, CSC3150 (Operating Systems)
      Jan. 2024 - May. 2024
    • Teaching Assistant, CSC3050 (Computer Architecture)
      Sep. 2023 - Dec. 2023
    • Teaching Assistant, MAT1008 (Advanced Mathematics)
      Sep. 2022 - Dec. 2022
Researching Experience
  • Federated Learning Research Intern
    Federated Learning Research Intern
    The Chinese University of Hong Kong, Shenzhen
    Topic: 'Federated Learning With Block Coordinate Descent'.
    Sep. 2023 - Dec. 2023
  • Neuromorphic Circuit Research Intern
    Neuromorphic Circuit Research Intern
    The Chinese University of Hong Kong, Shenzhen
    Topic: 'Neuromorphic Circuit Bitline Load Limit Estimation'.
    Aug. 2023 - Mar. 2024
Working Experience
  • OSA Student Journalists Association
    OSA Student Journalists Association
    The Chinese University of Hong Kong, Shenzhen
    Senior Web Operator & Executive Editor
    Sep. 2021 - Present
  • SSE Student Help Room
    SSE Student Help Room
    The Chinese University of Hong Kong, Shenzhen
    Preceptor for CSC1001 and CSC1002 (Python courses)
    Sep. 2023 - May. 2024
Selected Publications (view all )
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes

Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)

2nd International Symposium of Electronics Design Automation (ISEDA) 2024

The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

[Link] [PDF]

Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes

Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)

2nd International Symposium of Electronics Design Automation (ISEDA) 2024

The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

[Link] [PDF]