2024
Impacts of Parasitic Effects on PCM-based Neuromorphic Circuits under Advanced Technology Nodes
Xiaobao Zhu, Baokang Peng, Feilong Ding, Ziyu Xie, Yihan Chen#, Lining Zhang# (# corresponding author)
2nd International Symposium of Electronics Design Automation (ISEDA) 2024
The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.